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mriemleit's avatar
mriemleit
Icon for New Contributor rankNew Contributor
4 years ago

DDIO Output Timing Errors on a Source Synchronous Interface (RGMII)

Hi Intel Community, I've got problems with the timing of a RGMII Interface. In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally....
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Can you try with following constraint changes to the sdc?

1) Add create_clock constraint for the clk_in of the pll.

2) Add derive_pll_clocks

3) Remove create_generated_clock constraints as the derive_pll_clocks does the required job.


Regards


  • mriemleit's avatar
    mriemleit
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Ash,

    thanks for your time and help!

    I added 1) and 2) => I've still the same problem.

    3) I'm sorry but, I don't know what you mean.

    I've an output clock (RGMII125_TxClk) and the 90° shifted clock that is set on the output pin (RGMII1Data_TxClk). How can I tell the timing analysis to analyse setup and hold time, related to the clock at the output pin when I don't name them?

    The "create_generated_clock" statements are from page 10 of: an433.pdf

    The names are quite bad, so I updated them in the .sdc file:

    # create BaseClock
create_clock -name RGMII1_RxClk -period 125MHz [get_ports {pil_rgmii1_rxClk}]

# Generate 125 MHz Clock
create_generated_clock -name RGMIICLK_Data -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]}] [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}]

# Apply a generated clock to the clk_out port
create_generated_clock -name RGMIICLK_Clk -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[2]}] [get_ports {pol_rgmii1_txClk}]

derive_pll_clocks -create_base_clocks
derive_clock_uncertainty

set t(maxDelay) 1.0
set t(minDelay) -1.0

# Set output delay based on the requirements mentioned previously
set_output_delay -clock RGMIICLK_Clk -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMIICLK_Clk -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay

# Set false paths to remove irrelevant setup and hold analysis
set_false_path -fall_from [get_clocks RGMIICLK_Data] -rise_to [get_clocks RGMIICLK_Clk] -setup
set_false_path -rise_from [get_clocks RGMIICLK_Data] -fall_to [get_clocks RGMIICLK_Clk] -setup
set_false_path -fall_from [get_clocks RGMIICLK_Data] -fall_to [get_clocks RGMIICLK_Clk] -hold
set_false_path -rise_from [get_clocks RGMIICLK_Data] -rise_to [get_clocks RGMIICLK_Clk] -hold

set_false_path -to [get_ports {pol_rgmii1_txClk}]