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mriemleit's avatar
mriemleit
Icon for New Contributor rankNew Contributor
4 years ago

DDIO Output Timing Errors on a Source Synchronous Interface (RGMII)

Hi Intel Community, I've got problems with the timing of a RGMII Interface. In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally....
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Can you try with following constraint changes to the sdc?

1) Add create_clock constraint for the clk_in of the pll.

2) Add derive_pll_clocks

3) Remove create_generated_clock constraints as the derive_pll_clocks does the required job.


Regards