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mriemleit's avatar
mriemleit
Icon for New Contributor rankNew Contributor
4 years ago

DDIO Output Timing Errors on a Source Synchronous Interface (RGMII)

Hi Intel Community, I've got problems with the timing of a RGMII Interface. In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally....
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Sorry, that I could not spend enough time to this thread. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you