Forum Discussion
mriemleit
New Contributor
New ContributorDDIO Output Timing Errors on a Source Synchronous Interface (RGMII)
Hi Intel Community,
I've got problems with the timing of a RGMII Interface.
In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally....
Ash_R_Altera
Regular Contributor
Regular ContributorSorry, that I could not spend enough time to this thread. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
