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mriemleit's avatar
mriemleit
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4 years ago

DDIO Output Timing Errors on a Source Synchronous Interface (RGMII)

Hi Intel Community, I've got problems with the timing of a RGMII Interface. In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally....
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Could you please share sample Quartus design files where we see the timing errors? This will help us in debugging it better.

You may remove other custom logic if you will.


Regards


mriemleit's avatar
mriemleit
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4 years ago

Hi Ash,

here is the example project. I stripped everything except the RGMII Modul.

It would be great if you could point me in the right direction.

Many thanks in advance!

Best regards,

Michael