Data bus delay

Unfortunately you didn't show a time scale. Generally speaking, timing constraints can force the synthesis tools to give more importance to delay skew. But there will be a still an amount of PVT (process, voltage, temperature) induced variations.

If low bus delay skew is a design objective, you may want to enforce output registers.

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Hi,

I am designing a IP core. The output of the IP is 8bits data bus. When I do time silmulation ( vho + sdo ), I found data change in each bit of data bus are not at the same time. This is understandable that it is caused by path delay from source to destination. My question is: is there a good solution to solve this? How did you guys deal with this kind of issue?

see attached for the simulation waveform for better understanding.

thanks for any help.

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You 'solve' it by understanding that you never have a requirement for even two signals to switch simultaneously, there will always be a minimum and a maximum delay that is acceptable.

- You define this minimum and maximum to the synthesis tool by specifying timing constraints to the tool

- You verify that the minimum and maximum timing constraints have been met by review of the timing analysis report

- You ignore non-simultaneous changes that are all within the minimum and maximum since, by definition, they are acceptable to your design.

Kevin Jennings

--- Quote Start ---

Unfortunately you didn't show a time scale. Generally speaking, timing constraints can force the synthesis tools to give more importance to delay skew. But there will be a still an amount of PVT (process, voltage, temperature) induced variations.

If low bus delay skew is a design objective, you may want to enforce output registers.

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thanks, the data bus rate is quite low: 10M.

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You 'solve' it by understanding that you never have a requirement for even two signals to switch simultaneously, there will always be a minimum and a maximum delay that is acceptable.

- You define this minimum and maximum to the synthesis tool by specifying timing constraints to the tool

- You verify that the minimum and maximum timing constraints have been met by review of the timing analysis report

- You ignore non-simultaneous changes that are all within the minimum and maximum since, by definition, they are acceptable to your design.

Kevin Jennings

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Thanks Kevin, you give me a clear clue.