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Altera_Forum's avatar
Altera_Forum
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13 years ago

Data bus delay

Hi, I am designing a IP core. The output of the IP is 8bits data bus. When I do time silmulation ( vho + sdo ), I found data change in each bit of data bus are not at the same time. This is un...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Unfortunately you didn't show a time scale. Generally speaking, timing constraints can force the synthesis tools to give more importance to delay skew. But there will be a still an amount of PVT (process, voltage, temperature) induced variations.

If low bus delay skew is a design objective, you may want to enforce output registers.

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thanks, the data bus rate is quite low: 10M.