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Honored Contributor
Honored ContributorData bus delay
Hi, I am designing a IP core. The output of the IP is 8bits data bus. When I do time silmulation ( vho + sdo ), I found data change in each bit of data bus are not at the same time. This is un...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You 'solve' it by understanding that you never have a requirement for even two signals to switch simultaneously, there will always be a minimum and a maximum delay that is acceptable. - You define this minimum and maximum to the synthesis tool by specifying timing constraints to the tool - You verify that the minimum and maximum timing constraints have been met by review of the timing analysis report - You ignore non-simultaneous changes that are all within the minimum and maximum since, by definition, they are acceptable to your design. Kevin Jennings --- Quote End --- Thanks Kevin, you give me a clear clue.
