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You 'solve' it by understanding that you never have a requirement for even two signals to switch simultaneously, there will always be a minimum and a maximum delay that is acceptable.
- You define this minimum and maximum to the synthesis tool by specifying timing constraints to the tool
- You verify that the minimum and maximum timing constraints have been met by review of the timing analysis report
- You ignore non-simultaneous changes that are all within the minimum and maximum since, by definition, they are acceptable to your design.
Kevin Jennings
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Thanks Kevin, you give me a clear clue.
Honored Contributor
