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Honored Contributor
Honored ContributorData bus delay
Hi, I am designing a IP core. The output of the IP is 8bits data bus. When I do time silmulation ( vho + sdo ), I found data change in each bit of data bus are not at the same time. This is un...
Altera_ForumHonored Contributor
Honored ContributorUnfortunately you didn't show a time scale. Generally speaking, timing constraints can force the synthesis tools to give more importance to delay skew. But there will be a still an amount of PVT (process, voltage, temperature) induced variations.
If low bus delay skew is a design objective, you may want to enforce output registers.
