Altera_Forum
Honored Contributor
Honored ContributorDAC (DAC5672) and ADC (AD9254) in VHDL
Hi,
i have a project in which i need to create the VHDL code for a DAC (DAC5672) and an ADC (AD9254). It is part of a CDMA. The DAC must incorporate a 2's complement and the ADC must incorporate an offset binary. This is what i have so far : this is my adc which i am pretty sure will work ok : entity adc is port(clk : in std_logic;
adc_out : out std_logic_vector(13 downto 0);
analog_in : in std_logic_vector(13 downto 0)
);
end adc;
architecture behavioral of adc is
signal msb : std_logic;
begin
process(clk)
begin
if(clk'event and clk ='1') then
adc_out(12 downto 0) <= analog_in(12 downto 0);
msb <= analog_in(13);
adc_out(13) <= not msb;
end if;
end process;
end behavioral; this is my dac which i am pretty sure is no good : entity dac is port(
clk : in std_logic;
digi_in : in std_logic_vector(13 downto 0);
analog_out : out std_logic_vector(13 downto 0)
);
end dac;
architecture behavioral of dac is
signal analog_signal : std_logic_vector(13 downto 0);
begin
process(clk)
begin
if(clk'event and clk ='1') then
analog_signal <= digi_in;
analog_signal <= not(analog_signal) + "00000000000001"; -- complément à 2
end if;
end process;
analog_out <= analog_signal;
end behavioral; Please could someone point me in the right direction for either of the codes if they think something could be made better ? Thanks.
