DAC (DAC5672) and ADC (AD9254) in VHDL

Well, the code for the ADC controller is wrong. The msb of adc_out is delayed by and extra clock cycle compared to the rest of the word.

And in your ADC code, your analog_out is just a counter (that will actually not work in simulation). This is because you have assigned analog_signal to digi_in, but then overridden this assignment.. In VHDL, signals get assigned the last thing assigned to them. They are not like variables that are updated immedietly