Contributor
Regular ContributorHi,
Based on my understanding, you have questions regarding GX channel utilization in Cyclone V devices when the PCIe Hard IP is used. Please see the responses below.
Q1: Can all 6 TX/RX GXB channels be used when the PCIe Hard IP is enabled?
Answer: No. In all configurations, the PCIe Hard IP consumes the following resources:
As a result, from the total of 6 XCVR channel pairs:
Q2: Does the CMU PLL use CH5, and does that leave one extra channel for the PCIe Hard Core?
Answer: No. The CMU PLL is not fixed to CH5.
In Cyclone V devices:
Q3: What PCIe + custom GXB combinations are supported on a 6‑channel device?
Answer: The supported combinations depend on PCIe lane width and CMU PLL placement. Please refer to Figures 4‑5 through 4‑8 in the Cyclone V Device Handbook, Volume 2: Transceivers for the valid PCIe and custom GXB channel usage scenarios.
ContributorQ2: Does the CMU PLL use CH5, and does that leave one extra channel for the PCIe Hard Core?
Answer: No. The CMU PLL is not fixed to CH5.
In Cyclone V devices:
Only the channel PLLs in CH1 and CH4 can be reconfigured to operate in CMU PLL mode
I made a mistake on the number I do mean CH4 (0-5).
Q2' ) Based on the document: CMU PLL will use CH"""4""" and do this simply means there will be one extra for PCIe Hard-Core?
Based on Q2' it simply occupied 4+1.
Q2b) In order for custom protocol to run, a CMU PLL is required but due to hard PCIe CH1 already used by PCIe hard core while CH4 had forced to generate PLL clock for PCIe hard core.
So even there are 2 GXB remains; there is no way to feed in a custom protocol that is not PCIe speed i.e. PCIe GEN1 is 2.5Gbps?
Q2c) if not wrongly read from handbook; The GXB is split into up and bottom. Hence, the group can either [up + bottom] or individual [up | bottom] but either combine nor mix also require PLL to function?
Q3) If possible can the device simply feed by a Gbps/2 reference clock and then it simply disregard the needs of CMU PLL?
Additional info: I do more reading on the handbook it does clearly mentioned that the device is able to use fPLL to create the required clock rather than CMU PLL.
Based on the above information, I am still not sure the possibilities of using all GXB channel even there could be crossing between bottom and top group.
Thanks,
Brian
Regular ContributorHi,
Regarding your latest question, if you are using PCIe ×2 as shown in Figure 4‑5, the transceiver resources would be allocated as follows by default:
With this allocation, there are no remaining CMU PLLs available for the other channels within the same bank.
As a possible workaround, you may consider using fPLL(s) to drive the remaining channels. However, whether this approach is supported and can be successfully placed depends on the specific design constraints and routing availability. In this scenario, it is likely that two fPLLs would be required (1 for bottom 3 channels and another for top 3 channels), but this cannot be confirmed upfront.
To determine feasibility, I recommend creating a simple test design and running it through a Quartus Fitter compilation to verify whether the placement and routing can be successfully achieved.
Please let me know if you have any concerns or need further clarification.
Thank you.
