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Altera_Forum
Honored Contributor
Honored ContributorCyclone V SoC - Shared Memory Controller
Hi @all,
I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. I have seen something like that there must be set some registers in the HPS to open the connection, (like with the HPS<->FPGA bridges), but I don't get the preloader generated by my design run correctly. And if I set the registervalues in HPS by hand, nothing happend on this interface. Has anyone set up a system with the shared memorycontroller working and could give me a hint to the right direction?51 Replies
Altera_Forum--- Quote Start --- I've been searching for any pointers to enable read / write access of HPS ram from the FPGA but cannot find any example code. The rocket board link fails (even when I have logged into the rocket board site), could you confirm the link or (big ask) share your project? --- Quote End --- Link: http://www.rocketboards.org/foswiki/projects/myfirstmodule- Altera_Forum
Hi all
I had a test just now, succeed in transfering test data form FPGA to SDRAM controller. But it only works in bare metal now, i don't kown if it helps The steps : 1 , Launch Qsys, Add a FPGA-to-SDRAM interface in hps, select the avalon MM write-only mode 2. Edit a Write-burst Soft IP base on Avalon MM master interface, add it to Qsys and connect it to the f2h sdram data interface in setp1 3. After compiling, debug preloader in DS-5 , I see the test in the memory window. - Altera_Forum
Dear voroshazi!
I am student, I have just studied SocKit Cyclone V, my goal is to access FPGA SDRAM from HPS through HPS2FPGA AXI Bridge, I still don't know how to implement this project. Do you give me a device and related document. I am looking forward your response. Thank you so much! - Altera_Forum--- Quote Start --- Dear BadOmen, Here is a feedback for your comments as I promised. According to your previous post I have also managed to access now the FPGA SDRAM / internal BRAM from the HPS portion (ARM side) at HWLib level. The key was to release the bridges from reset (init_bridge in hwlib.c). However, without DMA I have measured only 10 - 15 MB/s memory throughput (between ARM vs. FPGA memory) across HPS2FPGA bridge. Do you suggest any reference design, which integrates (FW/SW) and uses DMA? What is the role the h2f_reset signal in HPS (cylcone V handbook gives a few info)? Because as I experienced if I left this signal unconnected in qsys I can use both FPGA memory and HPS memory in a same FW design? The debounce circuit is also eliminated from golden HW/SW reference design. "Address Span Expander" bridge will be a good IP in the future, but I set all memory address spaces to a narrower size in order to be accessed by a 32-bit addresses of Nios II processor. Regards, ZS.V. --- Quote End --- Dear voroshazi! I am student, I have just studied SocKit Cyclone V, my goal is to access FPGA SDRAM from HPS through HPS2FPGA AXI Bridge, I still don't know how to implement this project. Do you give me a device and related document. I am looking forward your response. Thank you so much!
- Altera_Forum
Also when using the FPGA-to-SDRAM ports after configuring the hardware I recommend writing to the applycfg bit as well which ensures the SDRAM port settings get set properly in the SDRAM controller. You can find this bit in the staticcfg register. You have to make sure the SDRAM controller is idle when writing to this bit so make sure you are executing code in another memory (on-chip RAM for example) when you write to the register.
- Altera_Forum--- Quote Start --- Link: http://www.rocketboards.org/foswiki/projects/myfirstmodule --- Quote End --- This is SW. However, is there any HW/SW combined example for FPGA-to-SDRAM interfaces?
- Altera_Forum--- Quote Start --- This is SW. However, is there any HW/SW combined example for FPGA-to-SDRAM interfaces? --- Quote End --- I have the same question.
- Altera_Forum
I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code!
- Altera_Forum
Hi -- I would really appreciate a copy of the example project. Apparently I don't have enough posts here to be able to PM you directly, but if you wouldn't mind sharing I would appreciate it.
Thanks Lance (lance @ RFdude.com ) - Altera_Forum--- Quote Start --- I've got a working HW/SW example project illustrating FPGA-HPS SDRAM interface verifiable from the FPGA side via System Console and from the ARM Linux side via devmem tool. PM me if you would like the Quartus Project and source code! --- Quote End --- Could you send me a copy of the project and the source code? My email is [email protected]. Thank you!
