Cyclone V SoC - Shared Memory Controller

Hi all

I had a test just now, succeed in transfering test data form FPGA to SDRAM controller.

But it only works in bare metal now, i don't kown if it helps

The steps :

1 , Launch Qsys, Add a FPGA-to-SDRAM interface in hps, select the avalon MM write-only mode

2. Edit a Write-burst Soft IP base on Avalon MM master interface, add it to Qsys and connect it to the f2h sdram data interface in setp1

3. After compiling, debug preloader in DS-5 , I see the test in the memory window.