Cyclone V SoC - Shared Memory Controller

Also when using the FPGA-to-SDRAM ports after configuring the hardware I recommend writing to the applycfg bit as well which ensures the SDRAM port settings get set properly in the SDRAM controller. You can find this bit in the staticcfg register. You have to make sure the SDRAM controller is idle when writing to this bit so make sure you are executing code in another memory (on-chip RAM for example) when you write to the register.