Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCyclone V SoC - Shared Memory Controller
Hi @all, I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This is SW. However, is there any HW/SW combined example for FPGA-to-SDRAM interfaces? --- Quote End --- I have the same question.
