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New ContributorCyclone V QSPI AS Configuration timing data
Hi,
We are using Cyclone V (5CGXFC7B6M15I7N) in on of our design. We are doing the timing budget analysis for QSPI NOR Flash interface (AS Configuration). FPGA datasheet shows the DATA[] hold time after rising edge on DCLK as '0 nS' (Page 76). Request you to provide the minimum hold time the FPGA holds the data after the DCLK rising edge, which will be helpful for the setup and hold time margin calculations with the Flash device.
Thanks
Sudheer.
Hi Sudheer,
You can use the 1.5nS. That will also protect you if you need to change to EPCQ-A device in the future because the EPCQ device is EOL (https://www.mouser.com/pcn/intel_corporation_pdn1708_rev_1.0.0.pdf).
There is not much functional difference between the two. I think Intel's supplier for EPCQ shut down so they had to create a new part and called it EPCQ-A.
Thanks,
Travis
14 Replies
TravisCovertOccasional Contributor
Hi Sudheer,
Please refer to the Device Handbook in the section on Evaluating Data Setup and Hold Timing.
Cyclone V Device Timing: https://www.intel.com/content/www/us/en/docs/programmable/683801/current/active-serial-as-configuration-timing.html
Here is a migration guide that can also help. https://www.intel.com/content/www/us/en/docs/programmable/683340/current/fpga-configuration-device-migration.html
Be careful when calculating the hold time. You might need to add a 10pF capacitor on the data lines if you cannot meet the hold time in the calculation.
If you look at the timing waveforms, the data is captured on the falling edge.
Thanks,
Travis Covert
SudheerVHi Travis,
Thanks for the update.
We have gone through the documentation that you have sent. We have calculated the data setup and hold time margins at FPGA.
To calculate the setup and hold time margins at the QSPI Flash we need the minimum data hold time requirement of the FPGA (During Flash Write cycle), which we are not able to get from the datasheet.
Thanks
Sudheer
- TravisCovert
Hi Sudheer,
For Flash Write operations the timing diagram should be in the flash datasheet.
Here is the timing waveform for the EPCQ flash.
Thanks,
Travis- SudheerV
Hi Travis,
Thanks for your reply. We are using EPCQ64SI16N in our product.
The read operation timing doesn't specify the minimum data hold time (after clock falling edge) requirement for data in the datasheet. Can you please help to provide this value. Datasheet gives only clock falling edge to data valid time.
Thanks
Sudheer
NurAiman_M_IntelSuper Contributor
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
