Cyclone V QSPI AS Configuration timing data

Hi Sudheer,

Please refer to the Device Handbook in the section on Evaluating Data Setup and Hold Timing.

https://www.intel.com/content/www/us/en/docs/programmable/683375/current/evaluating-data-setup-and-hold-timing.html

Cyclone V Device Timing: https://www.intel.com/content/www/us/en/docs/programmable/683801/current/active-serial-as-configuration-timing.html

Here is a migration guide that can also help. https://www.intel.com/content/www/us/en/docs/programmable/683340/current/fpga-configuration-device-migration.html

Be careful when calculating the hold time. You might need to add a 10pF capacitor on the data lines if you cannot meet the hold time in the calculation.

If you look at the timing waveforms, the data is captured on the falling edge.

Thanks,
Travis Covert

travis.covert@arrow.com

Hi Travis,

Thanks for the update.

We have gone through the documentation that you have sent. We have calculated the data setup and hold time margins at FPGA.

To calculate the setup and hold time margins at the QSPI Flash we need the minimum data hold time requirement of the FPGA (During Flash Write cycle), which we are not able to get from the datasheet.

Thanks

Sudheer

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