Forum Discussion
New ContributorCyclone V QSPI AS Configuration timing data
Hi Sudheer,
You can use the 1.5nS. That will also protect you if you need to change to EPCQ-A device in the future because the EPCQ device is EOL (https://www.mouser.com/pcn/intel_corporation_pdn1708_rev_1.0.0.pdf).
There is not much functional difference between the two. I think Intel's supplier for EPCQ shut down so they had to create a new part and called it EPCQ-A.
Thanks,
Travis
Occasional ContributorHi Sudheer,
For Flash Write operations the timing diagram should be in the flash datasheet.
Here is the timing waveform for the EPCQ flash.
Thanks,
Travis
New ContributorHi Travis,
Thanks for your reply. We are using EPCQ64SI16N in our product.
The read operation timing doesn't specify the minimum data hold time (after clock falling edge) requirement for data in the datasheet. Can you please help to provide this value. Datasheet gives only clock falling edge to data valid time.
Thanks
Sudheer
- TravisCovert
Hi Sudheer,
The rising edge data is in the EPCQ datasheet. The falling edge data is in the FPGA handbook, linked below.
The falling edge information is in the Cyclone V handbook. Please refer to the Device Handbook in the section on Evaluating Data Setup and Hold Timing.
Hope this helps.
Travis
- SudheerV
Hi Travis,
We have checked the FPGA hold up time from handbook. We are looking for the hold up time information from Flash side. Here i have attached the datasheet snapshots from Micron NOR flash (MT25QU512ABB8E12-0AUT TR). We need the similar timing information for the EPCQ64SI16N device.
Request you to check this and provide the information.
Thanks for your quick reply.
Thanks
Sudheer
- TravisCovert
Hi Sudheer,
That Micron flash supports Double Data Rate (read data on rising and falling edges). EPCQ does not.
Since the EPCQ does not read data on the falling edge, it does not care about the timing of the data signals on the falling edge.
The EPCQ reads data signal in WRITE mode so there are timing specs for rising edge in the EPCQ datasheet. However, the FPGA reads data signals during READ mode, and it reads the data on the falling edge. This is why there is timing data around the falling edge but not the rising edge in the FPGA datasheet.
Thanks,
Travis
