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FPGA3's avatar
FPGA3
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4 years ago

Cyclone V PCIe HIP is stuck at L0 state and no activity on tl_cfg_ctl & tl_cfg_add

Design Description:

•PCIe – I2C design.

•PCIe x1 Gen 1 with application side running at 62.5 MHz

•Porting the design from Xilinx Artix 7 device to Intel Cyclone V.

•Application side is programmable IO state machine that drives the I2C interface.

Failure Symptoms:

•LTSSM state – L0

•No activity in signal Tap on tl_cfg_ctl & tl_cfg_add

•PCIe config space shows Correctable errors and Unsupported request in the snapshot in previous slide.

•No activity on AVST interface

•Tx_st_ready is low

•PMA lock is high reset status are ok from the HIP

•We are not in a state where application can run as the tx_st_ready is always low.

5 Replies

  • FPGA3's avatar
    FPGA3
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    4 years ago

    I checked it, This signal is low in signal tap.

  • FPGA3's avatar
    FPGA3
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    4 years ago

    As suggested, I tried driving the npor with the pin_perstn signal but no change in the output.

    Me and Harris had a second call after few mins again and here is the conclusion from the call.

    Few pointers that we discussed in the second call after I tried the experiment quickly.

    1. The current reset status that we captured in the signal tap is correct. Since the signal is active high and not active low. So original output was correct.
    2. Since the design has already enumerated the it is out of reset.
    3. Reviewed the IP configuration and the Tool version with Harris.
    4. I have attached the ppt with design description and the signal tap file with all the signals captured value as requested by Harris
    5. Harris to review the files and the ppt and get back to us with nest steps.
    • RichardT_altera's avatar
      RichardT_altera
      Icon for Super Contributor rankSuper Contributor
      4 years ago

      As mentioned by Harris:

      I checked the signals in .stp file, they were probed in post-fitting mode which was not correct way since signals might be no exist after full compilation. After I changed to pre-synthesis way, we can find PCIe HIP works well like ‘tl_cfg_xxx’ are toggling and ‘tx_st_ready’ is high. Currently, the problem is in user logic, why user logic doesn’t send out packets on AVST TX interface. Customer will need to debug the user logic next.

      • RichardT_altera's avatar
        RichardT_altera
        Icon for Super Contributor rankSuper Contributor
        4 years ago

        With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

        Best Regards,
        Richard Tan

        p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.