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FPGA3's avatar
FPGA3
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4 years ago

Cyclone V PCIe HIP is stuck at L0 state and no activity on tl_cfg_ctl & tl_cfg_add

Design Description: •PCIe – I2C design. •PCIe x1 Gen 1 with application side running at 62.5 MHz •Porting the design from Xilinx Artix 7 device to Intel Cyclone V. •Application side is progra...
RichardT_altera's avatar
RichardT_altera
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4 years ago

As mentioned by Harris:

I checked the signals in .stp file, they were probed in post-fitting mode which was not correct way since signals might be no exist after full compilation. After I changed to pre-synthesis way, we can find PCIe HIP works well like ‘tl_cfg_xxx’ are toggling and ‘tx_st_ready’ is high. Currently, the problem is in user logic, why user logic doesn’t send out packets on AVST TX interface. Customer will need to debug the user logic next.

RichardT_altera's avatar
RichardT_altera
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4 years ago

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.