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Re: Cyclone V FPGA SPI Flash programming
Hi Yuan: There are 2 particular issues we are needing help with: 1. SPI Programming failure with JIC file. The device seems to be supported in the guide we looked up online. •Not able to program the SPI flash with JIC file •Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly. •Device is in AS mode - MX25L12833FMI-10Gi •Device configurations tried to generate JIC files are EPCS128, EPCQ128 & EPCQ128A 2. Adding SPI Programming support in the FPGA design Since this is a ported design Current design has SPI programmer RTls available what ways we can use that and assign to the IO since the IO’s are hardened we can’t assign them. Which Ips to use? Also i couldn't find any demo design for this. Any further info/discussion on this will be very helpful.Cyclone V FPGA SPI Flash programming
We are trying to support the SPI flash programming from our FPGA design ported over from Xilinx device. We couldn't find any demo design. Meanwhile we tried the JIC programming as well for the N23Q128A device but it failed with following error. Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.Re: Cyclone V PCIe HIP is stuck at L0 state and no activity on tl_cfg_ctl & tl_cfg_add
As suggested, I tried driving the npor with the pin_perstn signal but no change in the output. Me and Harris had a second call after few mins again and here is the conclusion from the call. Few pointers that we discussed in the second call after I tried the experiment quickly. The current reset status that we captured in the signal tap is correct. Since the signal is active high and not active low. So original output was correct. Since the design has already enumerated the it is out of reset. Reviewed the IP configuration and the Tool version with Harris. I have attached the ppt with design description and the signal tap file with all the signals captured value as requested by Harris Harris to review the files and the ppt and get back to us with nest steps.Cyclone V PCIe HIP is stuck at L0 state and no activity on tl_cfg_ctl & tl_cfg_add
Design Description: •PCIe – I2C design. •PCIe x1 Gen 1 with application side running at 62.5 MHz •Porting the design from Xilinx Artix 7 device to Intel Cyclone V. •Application side is programmable IO state machine that drives the I2C interface. Failure Symptoms: •LTSSM state – L0 •No activity in signal Tap on tl_cfg_ctl & tl_cfg_add •PCIe config space shows Correctable errors and Unsupported request in the snapshot in previous slide. •No activity on AVST interface •Tx_st_ready is low •PMA lock is high reset status are ok from the HIP •We are not in a state where application can run as the tx_st_ready is always low.
