Cyclone V FPGA SPI Flash programming

Hi, you may find the list of supported configuration flash at link below:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/configuration-support.html#intel-config-devices

Hi Yuan:

There are 2 particular issues we are needing help with:

1. SPI Programming failure with JIC file. The device seems to be supported in the guide we looked up online.

• •Not able to program the SPI flash with JIC file
• •Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
• •Device is in AS mode - MX25L12833FMI-10Gi
• •Device configurations tried to generate JIC files are EPCS128, EPCQ128 & EPCQ128A

2. Adding SPI Programming support in the FPGA design

• Since this is a ported design Current design has SPI programmer RTls available what ways we can use that and assign to the IO since the IO’s are hardened we can’t assign them.
• Which Ips to use?
• Also i couldn't find any demo design for this. Any further info/discussion on this will be very helpful.

Hi,

Please find my response below:

1. SPI Programming failure with JIC file. The device seems to be supported in the guide we looked up online.

•Not able to program the SPI flash with JIC file

•Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.

•Device is in AS mode - MX25L12833FMI-10Gi

•Device configurations tried to generate JIC files are EPCS128, EPCQ128 & EPCQ128A

Can you select MX25 when generating the JIC file?

Also, please check the following as stated in the link below:

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/msgs/msgs/epgme_device_siid_error.htm

2. Adding SPI Programming support in the FPGA design

Since this is a ported design Current design has SPI programmer RTls available what ways we can use that and assign to the IO since the IO’s are hardened we can’t assign them.

Which Ips to use?

Also i couldn't find any demo design for this. Any further info/discussion on this will be very helpful.

You cant assign and use the IO which is used as configuration pin. To do flash content updating, you may consider using our IP such as Serial Flash IP for AS mode.

https://www.intel.com/content/www/us/en/docs/programmable/683299/current/using-the-fpga-serial-flash-loader-ip-85096.html

Regards,

Bruce

Hi Bruce,

I dont see an option for MX25. Here is the snapshot.

Can you click the ... beside configuration devices? Then select MX25 inside.

It just gives me an option for EPCS, EPCQ. Check out the snapshot below.

which quartus version you are using? Can you try with latest quartus version?