New ContributorCyclone V LVDS simulation errors
Hello,
I'm running into simulation errors with a simple project instantiating a ALTLVDS_TX block on a cyclone V FPGA. Everything (admittedly not much) runs fine if I comment the block out... I also tried re-generating the IP with different ports / options, but didn't have any luck.
This is with Quartus 22.1 and questa 21.2.
I get the following error:
# vsim work.lvds_tb
# Start time: 09:49:13 on Jan 30,2023
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: $MODEL_TECH/../intel/vhdl/src/cyclonev/mentor/cyclonev_atoms_ncrypt.v(38): in protected region
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0.
# Error loading design
# End time: 09:49:15 on Jan 30,2023, Elapsed time: 0:00:02
# Errors: 1, Warnings: 0
Thanks for any help !
Since you are using Quartus Standard 22.1 version, I suggest to use Nativelink so that it will automatically compile your design, Intel IP, simulation model libraries, and testbench.
You may checkout the document and video here:https://www.youtube.com/watch?v=PmVVXQchv2c
The .qar project can be generated by going to Project > Achieve Project.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
