Forum Discussion
New ContributorCyclone V LVDS simulation errors
Since you are using Quartus Standard 22.1 version, I suggest to use Nativelink so that it will automatically compile your design, Intel IP, simulation model libraries, and testbench.
You may checkout the document and video here:https://www.youtube.com/watch?v=PmVVXQchv2c
The .qar project can be generated by going to Project > Achieve Project.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Super ContributorMay I know which simulation flow are you using? Nativelink or scripted simulation flow?
Could you provide the design .qar file so I could check it from my side? (you can generate the .qar file by achieving the project)
And please provide the steps you used to simulate the design and produce the error.
Best Regards,
Richard Tan
New ContributorHi Richard,
Thank you for your quick response. I wasn't able to find a .qar file in my project, but I uploaded my output directory.
I am not using Nativelink. I just started a questa work library and compiled my test bench along with the generated vho file from Quartus (attached).
I get the above error when I attempt to launch the test bench in Questa.
Best regards,
Sam Underwood
