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sousbois's avatar
sousbois
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Cyclone V LVDS simulation errors

Hello, I'm running into simulation errors with a simple project instantiating a ALTLVDS_TX block on a cyclone V FPGA. Everything (admittedly not much) runs fine if I comment the block out... I als...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Since you are using Quartus Standard 22.1 version, I suggest to use Nativelink so that it will automatically compile your design, Intel IP, simulation model libraries, and testbench.
You may checkout the document and video here:

https://www.intel.com/content/www/us/en/docs/programmable/683080/22-1/using-nativelink-simulation.html

https://www.youtube.com/watch?v=PmVVXQchv2c

The .qar project can be generated by going to Project > Achieve Project.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.