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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone V HS serial interface

Hi.

I need an advice in high speed serial interface implementation for Cyclone V GX.

I want connect my boards in next sequence: tx0 - > rx1_tx1 -> rx2_tx2 -> ...... -> rxn. Receiver_1 is connected with transmitter_0. Transmitter_1 sends data to receiver_2 etc. Receiver_1 and Transmitter_1 (Receiver_2 and Transmitter_2 etc.) must occupy same Cyclone V transceiver.

All transceivers are configured in 4-line mode with throughput of 10 Gbit/s.The data stream is increased from device_0 to device_N. Each device adds received stream of data and it's own data stream and transmits to the next device. Maximum data stream speed is 10 gbps (at the end of this device sequence).

Which IP is better for use in this realization?

I am going to use Custom PHY IP-core. I am sure that will not have any problem with transceiver configured in TX mode. But I have doubts about using the transceiver in RX mode.

Will I have any problem with correct data receiving in this mode? I see that there are 4 clock line for parallel data from receiver. How can I use one clock for all receiving lines?

Regards,

Andrei.

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Andrei,

    Note that the max data rate for Cyclone V GX is 3.125Gbps. Thus, if total throughput of 4 channels is 10G then there should be no issue with each one running at 2.5G. Custom PHY should be OK for this implementation.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks for your reply.

    Now we are starting board design. This question becomes actual again.

    Main problem in this question is connection between boards like in first post.

    Transceivers in this configuration must work without handshaking (any interface I implement will be without link-layer). I must synchronize transmitter and receiver in manual mode. I afraid shall get problem here. Also I don't sure in independent applying receiver and transmitter (must occupy one transceiver).
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Ideally there should not be issue with the board connection as long as the SI is meeting all the required specs. You should try check functional simulation before implementing.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Ideally there should not be issue with the board connection as long as the SI is meeting all the required specs. You should try check functional simulation before implementing.

    --- Quote End ---

    Thank for your reply. I will try to do this.

    I have one more question. I implement XAUI core (or Custom PHY core with 4 lines). It takes 4 transceivers channels plus 1 channel (clock select MUX + channel PLL + clock divider)? Why does design with four lines occupy 5 channels? What can I do to set this core for using four channels?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi andrei_hres,

    The additional channel used by the XAUI core is for the TX PLL. For your information, the transceiver channels required a TX PLL to generate clocks for the transmitter.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Hi andrei_hres,

    The additional channel used by the XAUI core is for the TX PLL. For your information, the transceiver channels required a TX PLL to generate clocks for the transmitter.

    --- Quote End ---

    Hi nic_@

    Does this mean that in chip with 9 transceivers I cannot implement XAUI and Custom PHY with 4 lines? For this purpose I need use chip with 12 transceivers?

    I try different settings for Custom PHY core and find that in my chip I can implement XAUI + 3 lines Custom PHY.

    Is there any configuration for transceivers when I can implement XAUI + 4 lines Custom PHY in chip with 9 transceivers?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi,

    To implement XAUI, you will need 4+1 channels which will occupy one transceiver bank. To implement 4 Custom PHY, you will need another 4+1 channels which mean another transceiver bank. Thus, you would need 12 transceivers device.

    Not sure if the Cyclone V can use fPLL for these Custom PHY. You can double check in the documentation. If yes, probably you can fit into 9 channels device.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    To implement XAUI, you will need 4+1 channels which will occupy one transceiver bank. To implement 4 Custom PHY, you will need another 4+1 channels which mean another transceiver bank. Thus, you would need 12 transceivers device.

    --- Quote End ---

    Thanks.

    --- Quote Start ---

    Not sure if the Cyclone V can use fPLL for these Custom PHY. You can double check in the documentation. If yes, probably you can fit into 9 channels device.

    --- Quote End ---

    I have read about this but I don't understand how use this option.

    Does this mean that I need connect PLL_REF_CLOCK port of Custom PHY to any Cyclone V device PLL output?

    Regards,

    Andrei
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I cannot find configuration in wich 4 lines Custom PHY core occupy only 4 transceiver's channels (It takes 5 channels). Is this real to do?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    For fPLL, I think you would need to use Native PHY instead of Custom PHY. In Native PHY, you should be able to find an option of using external TX PLL. Then connect the serial clock port of the Native PHY to the fPLL.