Cyclone V HS serial interface

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Ideally there should not be issue with the board connection as long as the SI is meeting all the required specs. You should try check functional simulation before implementing.

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Thank for your reply. I will try to do this.

I have one more question. I implement XAUI core (or Custom PHY core with 4 lines). It takes 4 transceivers channels plus 1 channel (clock select MUX + channel PLL + clock divider)? Why does design with four lines occupy 5 channels? What can I do to set this core for using four channels?