Cyclone V Core overpower effects

a) Operating the FPGA core above it's recommended operating voltage will reduce the life of the device. It's 'recommended' for good reason. Yes, I accept the absolute max ratings permit higher voltages to be applied to the pins, but no chip manufacturer, including Altera, are likely to support you if you run into problems.

b) Supplying VCCIO with 1.1V will clearly not damage the FPGA but will compromise it's ability to operate correctly. It'll not be able to operate at the fmax specified by Quartus; assuming it's able to operate it's I/O at all. I think (my feeling here, nothing quantifiable) the IO will operate at 1.1V quite happily at 1.1V and, providing you operate well below fmax, all may be well.

However, I would seriously question your need to save a voltage regulator. A solution to satisfy this need not be expensive. I accept if you're hand building a prototype you want fewer parts. However, as soon as it doesn't work properly - where do you start?

Regards,

Alex

Hi Alex,

(a) I thought operating the FPGA above it's absolute maximum voltage will reduce the lifetime, as stated in the Cyclone V device datasheet, not above the recommended voltage? There is a table that declares how much the lifetime will be reduced, e.g. the IOs can tolerate 3.8V for 100% lifetime calculation (=10 years), and 4.0V only for 1.5 years...

The problem that I foresee is that the timing calculation for the FPGA cells is not adequate, as with higher voltage the switching works faster, so I may encounter hold time problems that the timing analyzer won't see because that tool depends on the 1.1V setting, and I found no way to change that...

(b) Constraints to save that regulator are board space, component count, routing more planes, maybe in more layers, ... I would assume no electrical problems, too, but maybe slower switching times which can effect the calculated timing margin for round-trip-delays (I output the clock, the RAM outputs data based on that clock, and I read it in, but slightly later than when using 1.2V... But the LPDDR2-interface generated by the MegaWizard adjusts itself to the data delay so it should work independently of signal flight time and rise-/falltimes...).

So, seems that there is no possibility to get some information, e.g. how much percentage of fmax switching is possible if the IO voltage is lowered by x percent? Or to tell the timing analyzer that the core runs on a slightly higher voltage?

Any other thoughts?

Best regards,

Tobias

Hi Tobias,

you should consider this

- any assumptions about CV core timing with Vcc above specified 1.13V are void

- quite similarly, mobile DDR2 behaviour with supply voltage below 1.14 can't be predicted

- there must be a certain margin for power supply tolerances

VCCIO specifications are primarly a formal 5% band around the respective nominal voltage. Thus I expect that operating CV at 1.1V VCCIO is the lesser problem and won't necessarily involve a noticeable speed drop at all.

If saving switching regulators is your main objective, a 1.2 to 1.1 LDO could be considered. Still involving 9 % efficiency loss.

Regards,

Frank

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Hi,

(a) What effects do I have to consider if I power the FPGA core with 1.2V instead of 1.1V to save one voltage regulator? (BTW: 1.2V is far away from the absolute maximum rating of 1.43V...)

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Could you use a diode or two to get the FPGA core IO down nearer to 1.1V?

You'd need to work out the power rating for your anticipated I_core but it might be cheaper than a regulator.

Nial