Honored Contributor
Honored ContributorHi Alex,
(a) I thought operating the FPGA above it's absolute maximum voltage will reduce the lifetime, as stated in the Cyclone V device datasheet, not above the recommended voltage? There is a table that declares how much the lifetime will be reduced, e.g. the IOs can tolerate 3.8V for 100% lifetime calculation (=10 years), and 4.0V only for 1.5 years... The problem that I foresee is that the timing calculation for the FPGA cells is not adequate, as with higher voltage the switching works faster, so I may encounter hold time problems that the timing analyzer won't see because that tool depends on the 1.1V setting, and I found no way to change that... (b) Constraints to save that regulator are board space, component count, routing more planes, maybe in more layers, ... I would assume no electrical problems, too, but maybe slower switching times which can effect the calculated timing margin for round-trip-delays (I output the clock, the RAM outputs data based on that clock, and I read it in, but slightly later than when using 1.2V... But the LPDDR2-interface generated by the MegaWizard adjusts itself to the data delay so it should work independently of signal flight time and rise-/falltimes...). So, seems that there is no possibility to get some information, e.g. how much percentage of fmax switching is possible if the IO voltage is lowered by x percent? Or to tell the timing analyzer that the core runs on a slightly higher voltage? Any other thoughts? Best regards, Tobias
