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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone V Altera PLL Can't do 100 MHz.

Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 100 MHz to the rest of the design.

However I am having problems, I made a SDC and I am having timining problems, says my fmax of the ALT PLL output is 91.73 MHz.

I used to use altpll and everything used to work, but altppl is not compatible to Cyclone V so I have to use the Altera PLL.

What can I do? I've played a little bit with Quartus II configurations and the sdc file but it was useless...

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  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Thanks for your answer, which FPGA have you used? Did you connect more than one component to the F2H/H2F/H2F_LW bridge? I have the problem when I connect a DMA and the TSE Mac to the F2S bridge.

    --- Quote End ---

    Dear Aprado,

    For example:

    Several Altera DMAs inserted and tried on FPGA side, which utilized F2H bridge.

    The FPGA-SDRAM interfaces has not been used, yet.

    Target platform was Cyclone V SoC DB rev.D (5CSXFC6D6F31C6).

    TSE MAC : Why are not you use the HPS' EMAC instead of FPGA TSE_MAC?

    Zs.V
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    I have also a question: How you can re-assign FPGA pins at the your PCB design procedure without the usage of FPGA Pin planner. Unfortunately, I observed, that in all latest versions of Quartus (13.0 - 14.0) the Pin planner (Live checker) does not function properly :

    "

    Live I/O check is currently not supported by the "<name>" family.

    (ID: 168014)

    http://quartushelp.altera.com/14.0/master.htm#mergedprojects/msgs/msgs/efiochk_live_io_check_not_supported_for_family.htm

    "

    Regards,

    Zsolt

    --- Quote End ---

    Answer for my question:

    The "Early IO Assignment Analysis" or "IO Analysis before a compilation" might be an alternative solution instead of Live I/O checker.

    The "I/O Assignment analysis" (Pin Planner) was successfully tested for Cyclone V SoC.

    Moreover, Live IO check will not be supported in the current (14.0) and future release for Cyclone V.

    Zs.V.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thank you very much for your answer, unfortunately I have some custom IP which interfaces directly with the TSE MAC.

    Cheers

    --- Quote Start ---

    Dear Aprado,

    For example:

    Several Altera DMAs inserted and tried on FPGA side, which utilized F2H bridge.

    The FPGA-SDRAM interfaces has not been used, yet.

    Target platform was Cyclone V SoC DB rev.D (5CSXFC6D6F31C6).

    TSE MAC : Why are not you use the HPS' EMAC instead of FPGA TSE_MAC?

    Zs.V

    --- Quote End ---