Cyclone V Altera PLL Can't do 100 MHz.

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I have also a question: How you can re-assign FPGA pins at the your PCB design procedure without the usage of FPGA Pin planner. Unfortunately, I observed, that in all latest versions of Quartus (13.0 - 14.0) the Pin planner (Live checker) does not function properly :

"

Live I/O check is currently not supported by the "<name>" family.

(ID: 168014)

http://quartushelp.altera.com/14.0/master.htm#mergedprojects/msgs/msgs/efiochk_live_io_check_not_supported_for_family.htm

"

Regards,

Zsolt

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Answer for my question:

The "Early IO Assignment Analysis" or "IO Analysis before a compilation" might be an alternative solution instead of Live I/O checker.

The "I/O Assignment analysis" (Pin Planner) was successfully tested for Cyclone V SoC.

Moreover, Live IO check will not be supported in the current (14.0) and future release for Cyclone V.

Zs.V.