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Altera_Forum
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11 years ago

Cyclone V Altera PLL Can't do 100 MHz.

Hello, I am desiging a custom board based on the Altera Cyclone V board. I've changed the board oscillator from 50 MHz to 100 MHz. I am trying to make it go throught a PLL inside QSys and then feed 1...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Thanks for your answer, which FPGA have you used? Did you connect more than one component to the F2H/H2F/H2F_LW bridge? I have the problem when I connect a DMA and the TSE Mac to the F2S bridge.

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Dear Aprado,

For example:

Several Altera DMAs inserted and tried on FPGA side, which utilized F2H bridge.

The FPGA-SDRAM interfaces has not been used, yet.

Target platform was Cyclone V SoC DB rev.D (5CSXFC6D6F31C6).

TSE MAC : Why are not you use the HPS' EMAC instead of FPGA TSE_MAC?

Zs.V