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ShivaKi's avatar
ShivaKi
Icon for New Contributor rankNew Contributor
1 year ago

Cyclone V_5CEBA7F27C8N_LVDS and LVPECL Interface_Quartus tool Setting

Hello,

In Cyclone V 5CEBA7F27C8N design, we have a LVDS inteface and LVPECL interface.

-Cyclone V to generate LVDS output to external IC

-Cyclone V to receive LVPECL input from external IC.

Considering these two interfaces are implemented in same bank. For example, Bank 6A is operating at 2.5V and LVDS, LVPECL are implemented in Bank 6A.

1. In LVDS interface, there are 7 pairs of differential signal outputs. What is the I/O standard that should be assigned for these 14 pins (7 differential pairs) in Quartus tool? Please confirm

2. In LVPECL interface, there is 1 pair of LVPECL differential signal inputs. What is the I/O standard that should be assigned for these 2 pins (1 differential pair) in Quartus tool? Please confirm

Configuration
Generic Io
Programmable Logic Device

7 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago
    Hi,
    Cyclone V E has true LVDS TX buffers in all IO banks, can be used with 2.5 VCCIO. No external components required. For LVPECL RX, either DC coupling or AC coupling can be used depending on driver common mode voltage, refer to LVPECL termination schemes in device handbook and voltage specifications in datasheet.
    Selected IO standard should be LVDS and LVEPCL.
    Regards
    Frank
  • ShivaKi's avatar
    ShivaKi
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hello Frank,

    While setting the IO standard as "LVDS" for differential outputs and "LVPECL" for differential input signals, the Quartus tool is showing an error.

    Error context is :

    "Error (21179): Pins SIGNAL_P and SIGNAL_N form a differential pair and uses pseudo-differential output node.

    -However, these pins also have an I/O standard LVDS that cannot be supported by the pseudo-differential output node."

    Error (11802): Can't fit design in device

    Error (293001): Quartus Prime Full Compilation was unsuccessful. 10 errors, 230 warnings"

    Could you please let us know how to resolve this issue?

    Note: All differential pairs assigned with LVDS/LVPECL are showing same error

  • ShivaKi's avatar
    ShivaKi
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hello Team,

    Could you please provide an update on the above error

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    Hello,


    Do you assign the n-channel for LVDS pin manually? For your information, the pin will be created automatically by Quartus Pin Planner. You only need to assign this pin to physical pin number either through global assignment or using pin planner manually.


    Can you help to try first and report back the result?


    Regards,

    Aqid


  • ShivaKi's avatar
    ShivaKi
    Icon for New Contributor rankNew Contributor
    1 year ago

    Hello Aqid,

    We have not assigned pins for n differential pins and only assigned for p pins, and setting made for "DIFFERENTIAL 2.5-V SSTL CLASS I" standard, as no error is seen.
    Can we consider "DIFFERENTIAL 2.5-V SSTL CLASS I" as per above setting in place of LVDS and LVPECL standard settings? Please confirm.

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

    I am not sure why you can't set the I/O standard to LVDS/LPECL for those pins, but it was passed with DIFFERENTIAL 2.5-V SSTL CLASS I. Are you willing to share the design with us? If you need to share in private message let me know.