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Altera_Forum
Honored Contributor
Honored ContributorCyclone IV E, transferring data using serial port
Hello everyone,
In a nutshell I have the following FPGA: http://fpga.redliquid.pl/images/ep4ce6/1.jpg (FPGA Cyclone IV E, ECP4E6), and what I want to do is to use the serial port. I've been following the following tutorial: https://www.youtube.com/watch?v=7xj9dhvdcwu (My quartus 2 is version 17.1). As far as I know this tutorial should be adapted for my specific board. I'm quite new to FPGA, so I might get confused a bit. At 3:40 is where I get confused, it is my understanding I need to map the I/O of the UART module created using that procedure to the I/O of the RS232 on the board. I don't actually know what the correspondings pins are, and also I can't manage to find anything in the documentation, but I think it's me reading something in the wrong way. Can anyone help me with this? I'm sure it is a "silly" thing to do. (of course if you know a simpler procedure please share). My final goal would be practice a bit with serial port and later developing some arithmetic units and passing data using my pc. https://alteraforum.com/forum/attachment.php?attachmentid=15101&stc=1 Thank you19 Replies
Altera_ForumHi,
Your board does not have a USB interface/connector. You can use Hyperterminal and a serial port(RS232) on your board and establish the serial communication. Use Nios ii processor, on-chip memory, jtag Uart & uart(rs232 serial port) for qsys design. For more information refer to link below. http://my-fpga.blogspot.my/2011/02/using-rs232-on-niosii-processor.html Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
MRPNew Contributor
Dear Anand Raj Shankar
I am using CoreEP4CE6, Altera Core Board for my lab work. I am also trying to communicate with MATLAB through UART. So for configuration, can I use the same procedure shown in the following link http://my-fpga.blogspot.my/2011/02/using-rs232-on-niosii-processor.html .
I am very new to FPGA hardware and my background also does not match with electronics. Help me to configure my FPGA to communicate with MATLAB via UART.
Best regrads
MRP
- Altera_Forum
Is that tutorial adaptable for my board + windows 10 + quartus 17.1?
- Altera_Forum
Hi,
Yes, you can use. Google and search for some reference design and how to install Hyperterminal on windows 10. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum--- Quote Start --- Hi, Yes, you can use. Google and search for some reference design and how to install Hyperterminal on windows 10. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) --- Quote End --- I'm not concerned about hyperterminal but for the rest of the procedure. I'll give it a go and let you know.
- Altera_Forum
Hi again,
Can you explain or give a reference why I need to istantiate the Nios II and the SDRAM block? (I get of course why I need the UART bit). Is it because I need later to create the C program that process the inputs? - Altera_Forum
Is the configuration below fine? It doesn't seem to me it matches exactly the link you provided.https://www.alteraforum.com/forum/attachment.php?attachmentid=15105
- Altera_Forum
Hi,
Go through some basic training. https://www.altera.com/support/training/curricula.html Refer following Links. https://www.youtube.com/watch?v=nhfvwthr_ew https://www.youtube.com/watch?v=yetvltb4hm4 First, understand you board specification. Do you have onboard SDRAM, You can use on-chip ram instead of using SDRAM to avoid extra pin assignment work. To eliminate the error. Auto-assign the base address and interrupt from a system option from tools bar of qsys. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum
It does have an SDRAM. Just a silly question,once I create the HDL using the platform planner (I managed at last) before compiling how do I get the name of the entity to be used as top entity?
- Altera_Forum
Hi,
Go to project navigator -> Files ->select the required file(.qsys/.qip) ->right click and set as the top level entity. 1.If you qsys design is top then save the project and qsys design in the same name. 2.If you have to interface with own logic/top file than the top file and project name to be same and save the qsys design in some other name. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum
Hi Again,
It's going a bit better but I still have problems. My code doesn't compile... Errors below
There must be an issue with my platform design. I attach the picture with my current setting: https://www.alteraforum.com/forum/attachment.php?attachmentid=15110 Can you help me please?Error (170048): Selected device has 30 RAM location(s) of type M9K. However, the current design needs more than 30 to successfully fit Info (170057): List of RAM cells constrained to M9K locations Info (170000): Node
