Forum Discussion
ContributorCyclone IV drop in replacement confirmations
Hi Brian,
Agree on the long-term point. Bench power-up alone does not prove lifetime stress. The goal is to stay inside the documented connection / reservation rules, not only “it boots today.”
Q: Need more clarification on this: tri-state w/o pull-up or?
A: Yes. On the density where that ball is GPIO:
- In Quartus, reserve that pin specifically as "As inputs that are tri-stated" (no weak pull-up, no bus-hold). In the .pin file that shows up as RESERVED_INPUT.
- On the board, hard-tie it to 2.5 V (same net as VCCA for the density that needs that ball as power). Per AN 592 / unused-pin guidelines: RESERVED_INPUT may be connected to a high or low on the board.
- So, external hard-tie to 2.5 V + FPGA pin = input tri-stated, no pull-up. Not floating tri-state.
The Quartus migration + RESERVED_INPUT (tri-state, no pull-up) + hard-tie to 2.5 V guidance follows Altera’s published migration and unused-pin connection rules. It is the supported way to keep the pinout legal across densities. It is not a guarantee of long-term electrical behavior for a continuous 2.5 V level on a GPIO that sits in a 1.8 V (VCCIO) bank (for example with SSTL-18 / HSTL-18 on that bank). Absolute VI ≤ 3.6 V and a successful board bring-up do not by themselves prove lifetime margin.
Regular ContributorHi Brian,
Agree on the long-term point. Bench power-up alone does not prove lifetime stress. The goal is to stay inside the documented connection / reservation rules, not only “it boots today.”
Q: Need more clarification on this: tri-state w/o pull-up or?
A: Yes. On the density where that ball is GPIO:
- In Quartus, reserve that pin specifically as "As inputs that are tri-stated" (no weak pull-up, no bus-hold). In the .pin file that shows up as RESERVED_INPUT.
- On the board, hard-tie it to 2.5 V (same net as VCCA for the density that needs that ball as power). Per AN 592 / unused-pin guidelines: RESERVED_INPUT may be connected to a high or low on the board.
- So, external hard-tie to 2.5 V + FPGA pin = input tri-stated, no pull-up. Not floating tri-state.
The Quartus migration + RESERVED_INPUT (tri-state, no pull-up) + hard-tie to 2.5 V guidance follows Altera’s published migration and unused-pin connection rules. It is the supported way to keep the pinout legal across densities. It is not a guarantee of long-term electrical behavior for a continuous 2.5 V level on a GPIO that sits in a 1.8 V (VCCIO) bank (for example with SSTL-18 / HSTL-18 on that bank). Absolute VI ≤ 3.6 V and a successful board bring-up do not by themselves prove lifetime margin.
ContributorSo I will simply consider a alternative solution by ferrite-bead place close to ball VIA and simply DNP or P by BOM. A 0402 or 0201 should able to handle 100mA or range on 200mA while a 2.5V should be AUX analog supply.
This is a good QA and should help many C4 user to cont'd design with more robust rules set.
