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Altera_Forum
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13 years ago

Cyclone III PLL loses lock at >75C

I am using PLL reconfiguration. When the FPGA is powered up the PLL is loaded with different M, N and C values for the frequency I want to generate.

The PLL will lock below 75C but once it gets to 75C it loses lock.:confused:

I have filtered the PLL voltages with ferrite beads and have included caps on the filtered side of the beads.

Any ideas what would cause the PLL to lose lock at higher temps?

This is a "I" marked part so it should go to at least 85C.

Thanks a lot,

Ed

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    How are you measuring the 75C? and how are you getting your part up to that temp?

    Do you have a thermal couple right on the case of the part, or are you using the chamber temperature?

    The ambient temp near the part may easily be greater that 10C above chamber temperature, especially if the part is in a box under a heat shield with zero air flow.

    The junction temperature is what really matters, but that's hard to directly measure, so getting a case temp is your best bet. If you device is under a heat shield, with zero air flow the temp of the part may be significantly hotter than you expect based on your chamber temp.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I would rather expect bad signal quality of the input clock, unstable voltage regulators and switching noise in general as popular PLL lose-of-lock causes. Their effect can be temperature dependent in various ways.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    75C measured using thermocouple on the part.

    Input clk is oscillator quality is good, voltage regulator is OK, switching noise is hard to eliminate, I have reduced outputs to minimum current.

    Those were my thoughts too, thanks for the replies.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Input clk is oscillator quality is good, voltage regulator is OK.

    --- Quote End ---

    I was just referring to the "most popular" cases, of course without knowing any details of your design.

    Bad input clock signal quality can e.g. mean ringing edges due to unsuitable signal termination. Voltage regulator instability may show as a unsuspicious oscillation of low magnitude in a few 10 kHz range.

    If it's a problem of self generated (simulatneous switching) noise, reducing the drive strength should definitely have an effect.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I know this thread is pretty old, but I am having the same problem.

    I have a Cyclone III EP3C25F256I7 and when I reconfigure the PLL's M,N,C values to a certain value at high temperatures (65C), the PLL loses lock and doesn't recover.

    I have about 10 sets of M,N,C values I program the PLL too. Only 1 set of them will cause the PLL to lose lock and not recover. This only happens on 2/6 FPGAs I tested.

    There is no issue at room temperature and if I hit it with cold spray, it will recover lock as well.

    Any body experience something similar?