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Altera_Forum
Honored Contributor
Honored ContributorCyclone III PLL loses lock at >75C
I am using PLL reconfiguration. When the FPGA is powered up the PLL is loaded with different M, N and C values for the frequency I want to generate. The PLL will lock below 75C but once it gets t...
Altera_ForumHonored Contributor
Honored ContributorI would rather expect bad signal quality of the input clock, unstable voltage regulators and switching noise in general as popular PLL lose-of-lock causes. Their effect can be temperature dependent in various ways.
