Forum Discussion

Honored Contributor

13 years ago

Cyclone III PLL loses lock at >75C

I am using PLL reconfiguration. When the FPGA is powered up the PLL is loaded with different M, N and C values for the frequency I want to generate. The PLL will lock below 75C but once it gets t...

Altera_Forum

Honored Contributor

13 years ago

I would rather expect bad signal quality of the input clock, unstable voltage regulators and switching noise in general as popular PLL lose-of-lock causes. Their effect can be temperature dependent in various ways.

Forum Discussion

Cyclone III PLL loses lock at >75C

Recent Discussions

Avalon-ST configuration with Agilex 3 fails

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Operating temperature for 10M08DCF256A7G

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Download links not working