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Altera_Forum
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14 years ago

Cyclone III PLL loses lock at >75C

I am using PLL reconfiguration. When the FPGA is powered up the PLL is loaded with different M, N and C values for the frequency I want to generate. The PLL will lock below 75C but once it gets t...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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Input clk is oscillator quality is good, voltage regulator is OK.

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I was just referring to the "most popular" cases, of course without knowing any details of your design.

Bad input clock signal quality can e.g. mean ringing edges due to unsuitable signal termination. Voltage regulator instability may show as a unsuspicious oscillation of low magnitude in a few 10 kHz range.

If it's a problem of self generated (simulatneous switching) noise, reducing the drive strength should definitely have an effect.