Cyclone III PLL cascading - lack of information

Hi everyone!

I try to run a Design with two PLLs. The first one not reconfigurable, inclk from dedicated clock pin (100MHz), located in PLL1. The second one is reconfigurable, inclk from the first one (100MHz) via global clock network, located in PLL3. The first PLL works fine. The second one should output a clock signal to a general purpose IO Pin, but it doesn't!

I synthesized the design only using the reconfigurable PLL, directly fed from the dedicated clock pin. This works. So I'm sure, all inputs to the PLL entity (for reconfiguration and stuff) are connected correctly and the mif file for initial configuration is fine too.

PLL related warnings I get when I synthesize the version with both PLLs are:

- The input ports of the PLL <first PLL and 2nd PLL> are mismatched, preventing the PLLs to be merged

--> This is ok I guess, because I don't want them to be merged.

- PLL <reconfigurable PLL> input clock inclk[0] may have reduced jitter performance because it is fed by a non-dedicated input

- PLL <reconfigurable PLL> output port clk[0] feeds output pin "test1~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

--> Not nice, but I think both should not lead to NO output signal.

(The device is an EP3C16Q240C8)

Any ideas? I would be happy about every hint! Nor the Cyclone handbook neither an application note could help me so far.

Thanks in advance!