Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Cyclone III PLL cascading - lack of information

Hi everyone! I try to run a Design with two PLLs. The first one not reconfigurable, inclk from dedicated clock pin (100MHz), located in PLL1. The second one is reconfigurable, inclk from the first...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Finally... it works!

The only thing I had to do is to change the location of the reconfiguarable PLL from PLL 3 to PLL 2. This is reproducible. I did not use PLL specific stuff like differential clock output ports or such things. There is only one PLL output connected with a GPIO. So I wonder why the location of the PLL has an influence on the synthesis result.