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Altera_Forum
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15 years ago

Cyclone III PLL cascading - lack of information

Hi everyone! I try to run a Design with two PLLs. The first one not reconfigurable, inclk from dedicated clock pin (100MHz), located in PLL1. The second one is reconfigurable, inclk from the first...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

maybe you can try running the line between the PLL through clock buffer, that way the input to the second PLL might be considered as a dedicated line.