Cyclone III configuration

Funny post :)

The real story is that you CAN connect the JTAG pins via pull-up to 3.3V, but it is not recommended because the overshoot caused by the download cable may damage your FPGA. So if you are going to be really careful, go ahead and use 3.3V for JTAG.

If you decide to use the recommended 2.5V for JTAG though, you can still use 3.3V or whatever else VCCIO you need for any bank, including 1 and 6. Voltage level translators (especially the step-down ones) are really simple, use a resistor divider to get your 2.5V level CONF_DONE and whatnot :)

Read the ciii design guidelines (http://www.altera.com/literature/an/an466.pdf), page 22 onwards, for info about JTAG connections.

Edit: by the way, where did you get page 10-73 on the Cyclone III Handbook, my copy I downloaded just now stops at page 10-70 before jumping to 11-

Not using bank 1 & 6 at all is actually great news for your purposes!

Remember, just because you do not use a particular bank does not excuse you from powering each bank with some voltage!

In your case, just go ahead and connect the Vccio for those banks to 2.5 volts (as well as any other bank you are not planning to use.

Hope this helps.

No, it's the 2.5V I don't use anywhere - as a signalling level. I do use it for the VCCA and VCCD_PLLn pins. I need every pin I can get and will definitely use the IO banks 1 and 6.

_________

I had the older version of the databook which had a mistake which was corrected in the newer version.

The old version had us connecting the pull-up of the nSTATUS and CONF_DONE to the "same supply voltage as the USB-Blaster" the new version corrects this to "the VCCIO supply of the bank in which the pin resides".

This still leaves me with a 2.5V signalling environment on bank 1. As I said before I don't have any 2.5V signals on my board.

(To Clancy: What do you mean by "be really careful" with the USB Blaster?

It seems to me that either it blows up the FPGA's inputs or it doesn't, I don't see how I can be "really careful".)

Is there some way to add protection diodes to the JTAG signals and then use 3.3V for both the JTAG and Bank 1? ... or perhaps a buffer would be safer?

Recently I received prototype boards in which I attached the pull-ups for the TDI and TMS pins to 2.5V like page 10-73 note 6 says is appropriate for my ByteBlaster II. After having problems with the JTAG I started to do more research to find out that the JTAG pins reside in bank1 of the Cyclone III EP3C25F256 which I have tied to 3.3V. To appease the panic setting in, I wanted see in print that the JTAG port could be used at 3.3V with a CIII part. (The fix to make this port 2.5V would require disconnecting BGA pins from the power plane--much easier to connect my pull-ups to 3.3V) I found the following document on the Altera site which says 3.3V is acceptable. Unfortunately as far as I can tell this was missing from the configuration chapter (CH10) in the manual.

Chapter 14, Page 14-14

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices

http://www.altera.com/literature/hb/cyc3/cyc3_ciii51014.pdf

Hello,

when you read the Cyclone III handbook's configuration chapter, you could wonder, if the device is 3.3V tolerant at all, but from the maximum ratings, this is the case without doubt, including JTAG and configuration interface. Comparing Cyclone II and III maximum ratings, the margin for voltage overshoot versus time is clearly smaller, but the absolute maximum ratings are nearly unchanged. Thus a configuration circuit that could damage Cyclone III devices would also be harmful to Cyclone II and others, usually operating with 3.3V powered configuration, provided the datasheet values are comparable.

But a protection circuit for an external connected configuration interface is menaningful anyway, e. g. a 100 ohms series resistor with a dual schottky diode connected to GND/VCCIO. It should be able to guarantee the allowed AC and DC ratings for I/O oins, except with ESD pulses.

To my opinion, the new thing with Cyclone III configuration interface is the VCCA dependency and the issues arising when VCCIO is powered after VCCA or rising non-monotonically. I guess, Altera developers have been somewhat suprized, how much confusion at customers side could be caused by some simple design changes. Afterwards, they took the easy way and ordered that Cyclone III configuation should be powered by 2.5V VCCIO connected to VCCA, exclusively. This, by the way, would also reduce the danger of overshoot induced damages.

I think, this could actually be a good advice for completely new designs. But customer may have different motives to continue with mainly 3.3V VCCIO, e.g. continuation of existing designs or device stock. Altera application engineers should rather help the customer to realize their design requirements as far as possible than suggesting arbitrary changes.

Regards,

Frank

Hello,

I not sure, if I understand the question exactly. But the USB Blaster versions I know don't drive out voltage that isn't derived from target VCC (pin 4). Would be very surprized if this had been changed.

Regards,

Frank

This is what they say about interfacing a CIII device for AS or PS configuration. And it's confusing reading this thread which kinda suggest to use 2.5 V :rolleyes:

http://www.altera.com/support/kdb/solutions/rd10152007_741.html

Solution ID: rd10152007_741

Last Modified: Oct 30, 2007

Product Category: Devices

Product Area: Configuration

Product Sub-area: Active Serial (AS)

problem

How do I interface a Cyclone® III device with its configuration device in Active Serial or Active Parallel configuration scheme?

solution

in an active serial (as) configuration scheme for cyclone iii device, the vccio of i/o bank 1 must be 3.3v. In an Active Parallel (AP) configuration scheme for Cyclone III device, the VCCIO of banks 1, 6, 7 and 8 must be the same and must be either 1.8, 2.5, 3.0 or 3.3V.

altera® recommends that you do not use level shifters between a configuration device and the cyclone iii device in any active (as or ap) configuration scheme.

Can someone please clarify this. I wanna use the scheme in figure 10-29 :eek:

Hello,

using 2.5V for JTAG interface is an Altera suggestion from Cyclone III manual respectively AN466 cyclone iii design guidelines. It hasn't been invented in this thread. There are understandable reasons for this suggestion, but is also obvious that it doesn't fit all applications. Basically, configuration interface (including JTAG) can use VCCIO up to 3.3V as with previous devices if some precautions are observed.

With AS configuration, 3.3V VCCIO in the respective bank should be used, cause EPCS devices use 3.3V supply, the same with 3.3V standard flash in AP Mode. That's what the quoted knowledge base entry says.

With AS and CIII, you have two options: The traditional combined circuit, requiring separate configuration connectors for AS and JTAG, the AS part as shown in figure 10-28 or the new "smart" CIII variant, programming AS device through a SFL JTAG instance, as in figure 10-29. (I assume, that JTAG interface should be always present for development and test support) You may ask, why the two figures don't clearly set AS VCCIO to 3.3V as requested by the knowledge base? I don't know.

Regards,

Frank

Hi Frank

Thanks for the reply, couple more clarifications if possible. Again this is for AS as in figure10-29

1) because I'm using an EPCS device nSTATUS and nCONFIG should be pulled-up to 3.3V and the VCCIO for the bank where these pins reside should also be 3.3V?

2) CONF_DONE should be pulled up to VCCIO of the bank where the pin reside, in my case (2.5V)?

3) VCCA shown on figure 10-29 for the JTAG pull ups is 2.5V?

Thanks