Cyclone III configuration

Hi everyone,

To add to the confusion, I've made a couple of C3 designs (all with JTAG access, EPCS to be programmed with JIC files via JTAG instead of direct AS to save board space) before this thread was started. Here are the findings.

I made two identical, simple boards, 3.3V VCCIO for all banks including Bank 1. JTAG was referenced to 2.5V. One board worked fine from the get-go, no problems whatsoever. The second board was different. It just didn't want to configure, CONF_DONE stayed low. However, just touching CONF_DONE with a scope probe or even finger was enough to get it going. However, adding capacitance on the 3.3V line changed that, and that method didn't work anymore, neither did small capacitors to VCC etc. on CONF_DONE work. The solution came by shorting out nSTATUS to 3.3V VCCIO instead of the 10k pullup. Not even a 10ohm resistor worked, it had to be shorted. Now everything's fine.

On another design, Bank6 was 2.5V due to an LVDS clock interface and hence that bank's references were all to 2.5V. On that design, one prototype worked fine. On a subsequent revision, which had minimal changes and none to the configuration, it didn't want to access the JTAG. Checking the signals with a scope it's clear that the FPGA is continually trying to configure from the EPCS and after a few seconds "gives up". It boots fine from the EPCS if it's configured upon powerup. However, JTAG is inaccessible in such a steady-state, unless it's shortly after powerup (less than 5seconds). So, whenever I need to access JTAG for debugging or programming the EPCS (via JTAG), I just turn it off and on again, and quickly after powerup access the JTAG. Once the JTAG is accessed it's fine.

Any ideas?