Cyclone III configuration

Thank you for the suggestion. Your interpretation was absolutely correct, by the way. I'm happy, that you finally understood my intention and apologize for any inconvenience.

Actually, some boards have problems with Altera Blaster, some with Terrasic, some hadn't ever. They are all using 3.3V IO.

I don't think that the overshoot problem is directly related to failing configuration. It's an additional issue, some kind of overshoot of course may cause double clocking. The overshoot observed with Rev.B USB Blaser is a special one, not cause by cable reflections but the used Maxim level translator, to my opinion. The overshoot has several 10 ns duration, longer than any possible cable delay. I don't have Terasic or Altera Rev. C Blaster at hand, I'll check occasionally how their waveforms look like.

You may be right, that using 2.5 VCCIO could possibly increase double clocking effects. I never used 2.5V VCCIO and didn't consider it yet as a means to get a more reliable JTAG interface.

I recently experienced a JTAG problem, where an onboard signal apparently interfers with TCK. It caused occasional double clocking when both signal edges coincided. The issue could be solved by reducing the interfering signal's drive strength, which was unnecessecary high.