All, We have 30 boards with a single EP3c25 wired for JTAG and AS configuration, as per the handbook. Several pairs of eyes have peered at the schematic and the boards and everything looks like it should. But, on most of the boards, configuration with USBBlaster results no errors but a corrupt FPGA image in the chip. Multiple tries will usually result in one good configuration that allows us to program the EPCS. Once that is done the boards work reliably. Except that they are still as difficult to configure through JTAG as ever. The problem varies from board to board. Some are good, some are not so good and others are completely useless. Most of the boards are flaky to useless. All the voltages look good. JTAG signals look clean. The programming software generates no errors. CONFIG_DONE goes high even though the image is bad. (We can tell by LEDs on the board if the image took or not.) We've made Altera and Cyclone III boards before and have not had these kinds of problems. What could possibly be causing this?

Can you probe the INIT_DONE signal? Look at p56 (these are for PS/FPP, but the signals should do the same thing for JTAG configuration): http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf) Note how INIT_DONE goes low when programming starts, and then high again when done on p60. Note how there is a delay between CONF_DONE and INIT_DONE. I wonder if your FPGA is being left in the no-mans land between CONF_DONE going high and INIT_DONE going high. See p63 for enabling the INIT_DONE output. Cheers, Dave

--- Quote Start --- But, on most of the boards, configuration with USBBlaster results no errors but a corrupt FPGA image in the chip. --- Quote End --- Does "no error" mean, the AS image verifies correctly after programming? P.S.: How do you know, that the image is corrupted? It may be a case of unpredictlable design behaviour as well, e.g. due to asynchronous reset or PLL lock issues. I would activate the CRC output to decide if the image is actually corrupted.

As I understand it, CRC wouldn't help in this case: If the image is corrupted on download, the CRC would be computed on the corrupted image and tell you nothing. Remember, once the image has been saved into EPCS, we have no problem bringing the board up. It's ONLY through the JTAG that there's a problem.

Does anyone know where I can find the information about the sequence of commands that the JTAG issues to configure the chip?

--- Quote Start --- Can you probe the INIT_DONE signal? Look at p56 (these are for PS/FPP, but the signals should do the same thing for JTAG configuration): http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf) Note how INIT_DONE goes low when programming starts, and then high again when done on p60. Note how there is a delay between CONF_DONE and INIT_DONE. I wonder if your FPGA is being left in the no-mans land between CONF_DONE going high and INIT_DONE going high. See p63 for enabling the INIT_DONE output. Cheers, Dave --- Quote End --- I've checked. INIT_DONE toggles and goes high at the end, as it's supposed to.

Cyclone III configuration corrupts image | Altera Community

23 Replies

Altera_Forum
Honored Contributor
13 years ago
We come to the conclusion that it's a manufacturing issue, perhaps aided by a "less than optimal" layout. Since we now have a work-around, we're going to cross our fingers and hope the next design works better.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
We come to the conclusion that it's a manufacturing issue, perhaps aided by a "less than optimal" layout. Since we now have a work-around, we're going to cross our fingers and hope the next design works better.
--- Quote End ---

Is the 'next design' a completely difference design, or the same design with a cleaner PCB layout? Regardless, I would recommend you plan on creating a small run of prototype/pre-roduction boards, and confirm the issue has been resolved. I typically find that 5 boards is a good minimum number of boards, as it allows you to discard one or two boards with assembly related issues, and focus on the real problems.

Cheers,
Dave
Altera_Forum
Honored Contributor
13 years ago
I was just reading through this thread and wonder if you had the JTAG pull-ups and power on header pin 4 connected to 3.3V or 2.5V in your initial layout.

If so that's a possible issue. On Cyclone III the JTAG interface is based on VCCA which is 2.5V so that should the voltage connect to pin 4 of the header and used for the pull-ups on TDI and TMS.

I know we had issue with JTAG configuration when we had these connected to 3.3V on one of our boards.

See Figure 9-24 in the handbook. Note if the VCCIO is < 2.5V then these are connected to the VCCIO rail for the bank. as in figure 9-25

Forum Discussion

Cyclone III configuration corrupts image

23 Replies

Recent Discussions

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?

System PLL of Agliex5 PCIE example design cannot be locked after configuration

JTAG Chain Broken on Agilex 7-I Dev Kit

Request for Cyclone V Pinout File Information

Cyclone 10 LP's Extended Industrial parts