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Altera_Forum
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Honored ContributorCyclone III configuration corrupts image
All,
We have 30 boards with a single EP3c25 wired for JTAG and AS configuration, as per the handbook. Several pairs of eyes have peered at the schematic and the boards and everything looks like it should. But, on most of the boards, configuration with USBBlaster results no errors but a corrupt FPGA image in the chip. Multiple tries will usually result in one good configuration that allows us to program the EPCS. Once that is done the boards work reliably. Except that they are still as difficult to configure through JTAG as ever. The problem varies from board to board. Some are good, some are not so good and others are completely useless. Most of the boards are flaky to useless. All the voltages look good. JTAG signals look clean. The programming software generates no errors. CONFIG_DONE goes high even though the image is bad. (We can tell by LEDs on the board if the image took or not.) We've made Altera and Cyclone III boards before and have not had these kinds of problems. What could possibly be causing this?23 Replies
Altera_ForumI was just reading through this thread and wonder if you had the JTAG pull-ups and power on header pin 4 connected to 3.3V or 2.5V in your initial layout.
If so that's a possible issue. On Cyclone III the JTAG interface is based on VCCA which is 2.5V so that should the voltage connect to pin 4 of the header and used for the pull-ups on TDI and TMS. I know we had issue with JTAG configuration when we had these connected to 3.3V on one of our boards. See Figure 9-24 in the handbook. Note if the VCCIO is < 2.5V then these are connected to the VCCIO rail for the bank. as in figure 9-25- Altera_Forum--- Quote Start --- We come to the conclusion that it's a manufacturing issue, perhaps aided by a "less than optimal" layout. Since we now have a work-around, we're going to cross our fingers and hope the next design works better. --- Quote End --- Is the 'next design' a completely difference design, or the same design with a cleaner PCB layout? Regardless, I would recommend you plan on creating a small run of prototype/pre-roduction boards, and confirm the issue has been resolved. I typically find that 5 boards is a good minimum number of boards, as it allows you to discard one or two boards with assembly related issues, and focus on the real problems. Cheers, Dave
- Altera_Forum
We come to the conclusion that it's a manufacturing issue, perhaps aided by a "less than optimal" layout. Since we now have a work-around, we're going to cross our fingers and hope the next design works better.
- Altera_Forum--- Quote Start --- INIT_DONE doesn't seem to work when programming via JTAG, but once the image is burned into EPCS, it does. --- Quote End --- I assume that you're not telling the tool you're using an external CLKUSR? (Just a suggestion) --- Quote Start --- So, the issue of the day is: what kind of problem would go away when we raise the voltage from 2.5 to 3.3? --- Quote End --- The only voltages you have at 2.5V are the VCCA/VCCD voltages right? Do these voltages even need to be powered for the device to exit power-on-reset? (Check the handbook). Try not powering them at all and see what happens. Cheers, Dave
- Altera_Forum
nCE was reworked from 300 to 10K, from "Cyclone II device family pin connection guidelines PCG-01003-1.1" - and using 10K actually makes it work a little better.
INIT_DONE is enabled. So is CRC. (note what I said earlier) Interestingly, INIT_DONE doesn't seem to work when programming via JTAG, but once the image is burned into EPCS, it does. How do I know the image is corrupt? 1. The CRC light is on. 2. LEDs that are supposed to be off are on. 3. We can't talk to the NIOS inside the chip. So, the issue of the day is: what kind of problem would go away when we raise the voltage from 2.5 to 3.3? - Altera_Forum
What do you currently have on nCE? Why not tied it to ground via 0-Ohms?
Are you creating your configuration file to enable INIT_DONE? Otherwise your LED will not light up, and you might just think that your configuration failed. Cheers, Dave - Altera_Forum--- Quote Start --- I'm just trying to understand here: How could power-up conditions effect JTAG programming, many seconds after power on, but not effect programming via EPCS? --- Quote End --- If it was only happening on one board, you might be able to hypothesize that if say nCE was not connected, that it was 'low' enough at power on for EPCS configuration, but then floated high, so that JTAG configuration would not work. I'll look at the schematic page. Cheers, Dave
- Altera_Forum
I'm just trying to understand here: How could power-up conditions effect JTAG programming, many seconds after power on, but not effect programming via EPCS?
The relevant part of the schematic is attached. - Altera_Forum--- Quote Start --- Why should this work? What harm might we be doing to the chip? Anybody? --- Quote End --- Its a bit hard to comment without seeing the design. Can you post the schematics? Have you probed the power rails and looked at their power-on timing and sequence relative to each other? Have you checked the errata? Have you looked at the clock signals on the board, are there glitches/reflections on anything, eg., the JTAG clock, DCLK, the core clock. If voltages and clocks are all within spec, then you should not have any issues. Where did you buy the devices? Are you sure the devices have not been pulled from boards, re-packaged, and re-sold? Try a part purchased through another distributor. Cheers, Dave
- Altera_Forum
Two turns of the board later, we still have a problem.
I enabled CRC and see a CRC error on the bad downloads, so the image is indeed corrupt. One thing we discoverd by accident is that if we connect 3.3v to the 2.5 rail, the board works like a champ. We've tried this on several boards and not only do the program but, in all ways, seem just fine. Why should this work? What harm might we be doing to the chip? Anybody?
