Cyclone III and 2xSDRAM

I need to open topic because I couldn't find answers anywhere so maybe someone can help.

Card is designed around EP3C40F484C6N with 2 SDRAM chips IS42S16320B-6TL but they are connected on opposite sides of FPGA.

Goal was to create 32bit interface but without sharing signals(ADDR and such like normal 32bit interface should be).

Idea was to be able to control each chip better by direct interface to the FPGA and now I see that this was bad idea.

Running LFSR tests on both chips is possible up to 80MHz but after that all fails.

First problem is that each SDRAM_CLK uses his own PLL so there might be problems with that.

SDRAM1_CLK is connected to PLL_4 and SDRAM2_CLK to PLL3.

To avoid Quartus using random PLL I did this in *.qsf:

--- Quote Start ---

set_location_assignment PLL_4 -to "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1"

set_location_assignment PLL_3 -to "pll2:pll2|altpll:altpll_component|pll_altpll:auto_generated|pll1"

--- Quote End ---

This says that 2 PLLs are generated who needs to be in sync. As I know they should be in sync by default but maybe there is something I don't know.

After that I have edited SDC file and added there what's needed to separate both chips.

INPUT SIGNALS

--- Quote Start ---

create_generated_clock -name sdram_clk -source [get_pins {pll|altpll_component|auto_generated|pll1|clk[2]}] [get_ports sdram_clk_o];

create_generated_clock -name sdram2_clk -source [get_pins {pll2|altpll_component|auto_generated|pll1|clk[0]}] [get_ports sdram2_clk_o];

set input_clock [get_clocks sdram_clk];# Name of input clock

set input_clock2 [get_clocks sdram2_clk];# Name of input clock

set tco_max 5.800; # Maximum clock to out delay (external device)

set tco_min 3.200; # Minimum clock to out delay (external device)

set trce_dly_max 0.240; # Maximum board trace delay

set trce_dly_min 0.200; # Minimum board trace delay

set input_ports [get_ports {sdram_dq_io[*]}];# List of input ports

set input_ports2 [get_ports {sdram2_dq_io[*]}];

# Input Delay Constraint

set_input_delay -clock $input_clock -max [expr $tco_max + $trce_dly_max - $trce_dly_min] $input_ports;

set_input_delay -clock $input_clock -min [expr $tco_min + $trce_dly_min - $trce_dly_max] $input_ports;

set_input_delay -clock $input_clock -max [expr $tco_max + $trce_dly_max - $trce_dly_min] $input_ports2;

set_input_delay -clock $input_clock -min [expr $tco_min + $trce_dly_min - $trce_dly_max] $input_ports2;

# set_multicycle_path -setup -from $input_clock -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 2

set_multicycle_path -from [get_clocks {sdram_clk}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -hold -end 2

--- Quote End ---

OUTPUT SIGNALS

--- Quote Start ---

set fwclk [get_clocks sdram_clk];# forwarded clock name (generated using create_generated_clock at output clock port)

set fwclk2 [get_clocks sdram2_clk];

set tsu 1.500; # destination device setup time requirement

set thd 0.800; # destination device hold time requirement

set trce_dly_max 0.240; # maximum board trace delay

set trce_dly_min 0.200; # minimum board trace delay

set output_ports [get_ports {

sdram_cke_o

sdram_csn_o

sdram_rasn_o

sdram_casn_o

sdram_wen_o

sdram_dq_io[*]

sdram_ba_o[*]

sdram_a_o[*]

sdram_dqm_o[*]

sdram_dq_io[*]

}]; # list of output ports

set output_ports2 [get_ports {

sdram2_cke_o

sdram2_csn_o

sdram2_rasn_o

sdram2_casn_o

sdram2_wen_o

sdram2_dq_io[*]

sdram2_ba_o[*]

sdram2_a_o[*]

sdram2_dqm_o[*]

sdram2_dq_io[*]

}]; # list of output ports

# Output Delay Constraints

set_output_delay -clock $fwclk -max [expr $trce_dly_max + $tsu - $trce_dly_min] $output_ports;

set_output_delay -clock $fwclk -min [expr $trce_dly_min - $thd - $trce_dly_max] $output_ports;

set_output_delay -clock $fwclk -max [expr $trce_dly_max + $tsu - $trce_dly_min] $output_ports2;

set_output_delay -clock $fwclk -min [expr $trce_dly_min - $thd - $trce_dly_max] $output_ports2;

--- Quote End ---

Next problem is this and could be related to phase shift coz for both chips needs to be different. On SDRAM1 all traces are 28mm, all but CLK who is 23mm. However on SDRAM2 all traces are also 28mm, only CLK is 14mm. This complicates things even more and right now I don't see option how to solve this. If someone is willing to discuss this serious complication I would really appreciate. If there is need for more data i can provide.