Honored Contributor
Honored ContributorHi, thank you a LOT for your reply! I m using controller my friend did but we stuck.
What is interesting here is when I run tests on one SDRAM chip it goes even more than 166MHz and behaves stable but problem is to run them together at that freq. Like I mentioned I think that problem is that each SDRAM uses different PLL and that clock traces are also different. Can you point me somewhere to read or what to do, what to investigate first. PLLs are using 7MHz source so since 2 PLLs are generated question is are they in sync, if they are not how to make them? I m talking about clk from FPGA to SDRAM. Next question is about phase shift because I think that each SDRAM for each PLL used needs different shift.
