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Altera_Forum
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16 years ago

Cyclone II Max Clock Rate

Hi all,

I am new to FPGA design and I am trying to get the most from my chip (EP2C20F484C7N). I have tried searching but everywhere seems to say different with no real reason to why that is the max rate.

In the datasheet from what I can see the max clock is 260Mhz.

However, I have found information to hint that it can go higher than this. For example, using both the rising and falling edge of the clock, PLL etc..

Can anyone share information on this?

Regards, Alan.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The max clking of an fpga is dependant on several things e.g. the fpga itself(including flipflop technology, routing...and other electrical level stuff that belongs to silicon people.) as well as the field engineers skill, design density speed density and the design itself(dedicated blocks usage and so on).

    It also may vary with different sections of same fpga.

    It is therefore hard for vendors to state exact figures but they only give an idea and in a comparative approach.

    The notion of using both edges is a trick to overcome clk speed limitation, usefull on board. You pass data at double clk speed onto two sets of registers but inside fpga ultimately a double clk is needed(clking one set of registers) to process data in their order.

    Your question on PLL: this is a different issue, you may generate fast clk but you need fpga to support that speed.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    In the datasheet from what I can see the max clock is 260Mhz.

    --- Quote End ---

    Seems like you stopped reading the device manual at the first "MHz" value...

    Actually the said 260 MHz value is a clock rate specification of Cyclone II embedded RAM.

    You also have maximum core clock (internal register clocking), input and output toggle rate for different IO standards and PLL clock frequency specifications. Unfortunately your question can't be related to a particular timing specification.

    To get a basic understanding of achievable FPGA performance depending on intended logic complexity, you should refer to Table 5-15 cyclone ii performance.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for your reply guys.

    I think PLL is what I am after here, I am trying to do algorithm work. I dont depend on external components (expect clock). So just logic elements?

    Like I said I am using EP2C20F484C7N, Speed grade -7 and currently a 50Mhz clock.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I would start of by ignoring the clock rate and putting down some logic. There's a decent chance the design is going to be topping out around that speed anyway. It is possible to do rise->fall->rise transfers to get more work done, but not done very often. If there isn't a feedback path within that logic, just get rid of the middle falling-edge register and the same amount of logic will be done between registers. (And there's no way you'll be getting 520Mbps rates in that part, so you'll most likely be running much slower probably 200MHz or less, with occasional burst that are faster.)

    But really start designing your HDL and you'll probably find other issue. The clock tree FMAX seldom comes into play except for the occasional small slivers of logic.