Cyclone II Max Clock Rate

I would start of by ignoring the clock rate and putting down some logic. There's a decent chance the design is going to be topping out around that speed anyway. It is possible to do rise->fall->rise transfers to get more work done, but not done very often. If there isn't a feedback path within that logic, just get rid of the middle falling-edge register and the same amount of logic will be done between registers. (And there's no way you'll be getting 520Mbps rates in that part, so you'll most likely be running much slower probably 200MHz or less, with occasional burst that are faster.)