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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cyclone II glitch on clock

Hi,

i have a cyclone II fpga. I'm using two asynchronus clock sources. These clocks are connected into the dedicated clock input of the chip (CLK0 and CLK2).

CLK0 is much faster than CLK2 (100MHz vs 300Khz). Both are rising edge clocks.

CLK0 control many I/O banks, CLK2 control a state machine.

When CLK0 change the status of the I/O banks, sometimes the state machine change his status on the falling edge of CLK2. With the oscilloscope i cannot see any glitch on CLK2 line, but there is...

It's possible have a more robust input?

P.S. if CLK0 don't control the I/O banks, everything is ok.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    if the CLK0 is PLL generated clock, take care on Power of PLL might help. it happens before to one of my poor friend, the PLL is not lock successful if power is not good.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi, both are external clock.

    CLK0 is generated by an oscillator, CLK2 by a microcontroller.

    CLK2 is a not periodic square waveform. When microcontroller is ready to trasnfert data, pull the CLK2 line (is a enable bit). On the rising edge the data is trasnferred.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    It's not actually clear from your post, how CLK2 "control a state machine". If it's actually the clock for the state machine process, then a ringing clock signal would be the most likely explanation. for the observed behaviour.

    I wonder, why you don't use an asynchronous edge detection for CLK2 instead? It would suppress all gliches smaller than 10 ns, if neccessary, a filter of multiple clock periodes could be added. This would also remove all synchronization problems between the clock domains.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    It's not actually clear from your post, how CLK2 "control a state machine". If it's actually the clock for the state machine process, then a ringing clock signal would be the most likely explanation. for the observed behaviour.

    --- Quote End ---

    It's the clock.

    --- Quote Start ---

    I wonder, why you don't use an asynchronous edge detection for CLK2 instead? It would suppress all gliches smaller than 10 ns, if neccessary, a filter of multiple clock periodes could be added. This would also remove all synchronization problems between the clock domains.

    --- Quote End ---

    What is an asynchronus edge detection?

    Is sampling CLK2 with CLK0? And what can i do to prevent metastability? 

    
PROCESS (CLOCK100)
BEGIN
if rising_edge (clock100) then
 clk2_b <= clk2;
 clk2_sync <= clk2_b;
end if;
END

    With this code clk2_sync is glitch free and not metastable?

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    So a workable code example is like this? 

    
PROCESS (CLOCK100)
BEGIN
if rising_edge (clock100) then
 clk2_b <= clk2;
 clk2_sync <= clk2_b;
end if;
END
PROCESS (CLOCK100, clk2_sync)
BEGIN
if rising_edge(clock100) then
last <= clk2_sync;
if (clk2_sync ='1' and last = '0') then
  clk2_enable = '1';
else
  clk2_enable = '0';
end if;
end if;
END PROCESS;
STATE_MACHINE: PROCESS (CLOCK100, clk2_enable)
 if rising_edge (clock100) then
   if clk2_enable = '1' then
     ...

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The basic idea is to use CLK0 only and generate a clock enable from CLK2.

    The below example uses a double synchronization register to consider for metastability, as suggested in the Quartus Software Handbook, although it's possibly not actually needed (the likelihood of metastable events is sometimes overestimated). 

    process (clok0)
begin
  if rising_edge(clk0) then
    clk2_s1 <= clk2;
    clk2_s2 <= clk2_s1;
    clk2_prev <= clk2_s2;
    if clk2_prev = '0' and clk2_s2 = '1' then
    -- action on clk2 rising edge
    end if;
  end if;
end process;