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Honored Contributor
Honored ContributorCyclone II glitch on clock
Hi, i have a cyclone II fpga. I'm using two asynchronus clock sources. These clocks are connected into the dedicated clock input of the chip (CLK0 and CLK2). CLK0 is much faster than CLK2 (100MH...
Altera_ForumHonored Contributor
Honored Contributorif the CLK0 is PLL generated clock, take care on Power of PLL might help. it happens before to one of my poor friend, the PLL is not lock successful if power is not good.
